Senior ASIC Digital Design Engineer (DDR) Full Time

Job Description

Job Requirements:

Synopsys is hiring a Senior Expert ASIC Digital Design Engineer to develop digital RTL Verilog designs with focus on DDR. 

In this role you will be responsible for:

• Generating and reviewing design specifications, developing implementation architectures
• Developing, coding, debugging, maintaining, and supporting RTL for significant portions of our designs.
• Generating documentation for customers, circuit development, test planning, verification environments, and usage.

Ideal candidate will:  

• Have a passion for creating solutions with a strong interest to continue being the best in the world at what we do.
• Have 8+ years of expert experience in digital RTL development and debugging, with an unyielding drive to take responsibility for increasingly complex designs. 
• Possess a strong desire to learn and explore new technologies;
• Demonstrate good analysis, communication, and problem-solving skills
• Have prior knowledge of and experience in ASIC design and associated development environments.
• Be fluent in synthesizable Verilog, comfortable with Perl, familiar with C, and experience with digital simulation and debug using industry-standard tools.

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Tagged as: c#, Coding, debug, Debugging, developing, digital simulation, Information Technology, maintaining, Perl, Senior ASIC Digital Design Engineer (DDR), supporting RTL, Synthesizable Verilog, System Programming